The present invention generally relates to a data processing processor, and more specifically, relates to a data processing processor containing a bus arbitrating apparatus capable of selecting one channel with respect to bus access requests issued from a plurality of channels.
Conventionally, as a bus arbitration control scheme for selecting one apparatus in response to bus use requests issued from a plurality of apparatuses to allow the selected apparatus to use the bus, one conventional bus arbitration control system is described in JP-A-3-263158. FIG. 3 schematically shows a major arrangement of this conventional bus arbitration control system. That is, as shown in FIG. 3, an information processing apparatus is arranged by a bus 51 used to commonly transfer information; at least two sets of apparatuses having bus control functions, for example, bus masters such as a central processing unit 52, and input/output control apparatuses 53/54; and a bus arbitration control apparatus 55. The bus arbitration control apparatus 55 of this conventional information processing apparatus owns such a control function. That is, in this conventional information processing apparatus, at least one timer 56, 57, 58, and a storage unit for storing thereinto an initial value of this timer are provided every bus master in the bus arbitration control apparatus 55. The bus acquisition waiting allowable time for each of the bus masters is stored in each of the storage units. When bus use requests are notified from the bus masters to the bus arbitration control apparatus 55, the countdown operations of the timers 56, 57, 58, for the relevant bus masters are commenced. When the bus is brought into usable condition, in such a case that at least two bus use requests are issued from the bus masters, while the respective timer values for the bus masters are compared with each other, this bus arbitration control apparatus 55 allows such a bus master having a minimum count value of a timer to use the bus, and also stops the count-down operation of the timer for the bus master which is allowed to use the bus so as to return the count value to the initial value. As a result, the bus use priority degrees for the respective bus masters are automatically increased in connection with such a fact that the bus acquisition waiting time of the respective bus masters is prolonged, so that the bus arbitration suitable for the respective bus masters can be controlled in a proper manner.